ultraedit wordfile for vhdl

/L15"VHDL" Line Comment = -- Nocase String Chars = " File Extensions = VHD VHO
/Delimiters = ~!@$%^&*()+=|\/{}[]:;""<> ,.?/
/Regexp Type = Perl
/Function String = "^\s*(\w*\s*:\s*process)"
/Function String 1 = "^\s*(entity\s+\w+)\s+is"
/Function String 2 = "^\s*(architecture\s*\w+\s+of\s*\w+)\s+is"
/Function String 3 = "^\s*(component\s*\w+)"
/Function String 4 = "^\s*(\w+\s*:\s*\w+)\s*$"
/Function String 5 = "^\s*(\w+\s*:\s*\w+)\s+port\s+map"
/Open Fold Strings = "(""process""if""loop" "component" "entity" "architecture"
/Close Fold Strings = ")""end process""end if""end loop" "end component""end entity" "end architecture"
/Open Brace Strings = "{" "(" "["
/Close Brace Strings = "}" ")" "]"
/C1"VHDL reserved words"
abs access after alias all and architecture array assert attribute
begin block body buffer bus
case component configuration constant
disconnect downto
else elsif end entity exit
file for function
generate generic group guarded
if impure in inertial inout is
label library linkage literal loop
map mod 
nand new next nor not null
of on open or others out
package port postponed procedure process pure
range record register reject rem report return rol ror
select severity signal shared sla sll sra srl subtype
then to transport type 
unaffected untis until use
variable
wait when while with 
xnor xor
/C2"VHDL attributes"
active ascending ascending 
base 
delayed driving driving_value
event 
falling_edge
high 
image instance_name 
last_active last_event last_value left leftof length low 
path_name pos pred 
quiet 
reverse_range right rightof rising_edge
simple_name stable succ 
transaction 
val value
/C3"VHDL stings"
""
/C4"VHDL types"
bit bit_vector boolean 
character
integer
line
natural
positive
real
signed std_logic std_logic_vector string
text time
unsigned
/C5"VHDL Procedures"
endfile
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