systemverilog wordfile

copied from http://avm-users.googlegroups.com/web/systemverilog.txt?hl=en&gsc=Lb4u6AsAAADWzOiV2TvclJOPyNlia6Gs
/L20"Verilog 1364-2001" Line Comment = // Block Comment On = /* Block Comment Off = */ String Chars = " File Extensions = SV SVL/Delimiters = ~!@%^&*()-+=|\/{}[]:;"<> , .?#/Function String = "%[a-z0-9]+[ ^t]+[a-z_0-9]+[ ^t]+("
/Indent Strings = "begin" "fork" "specify" "config"
/Unindent Strings = "end" "join" "join_any" "join_none" "endspecify" "endconfig"
/C1"Keywords"
alias always always_comb always_ff always_latch and assert assign assume automatic 
before begin bind bins binsof bit break buf bufif0 bufif1 byte
case casex casez cell chandle class clocking cmos config const constraint context continue cover covergroup coverpoint cross
deassign default defparam design disable dist do
edge else end endcase endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endspecify endsequence endtable endtask enum event expect export extends extern
final first_match for force foreach forever fork forkjoin function
generate genvar
highz0 highz1
if iff ifnone ignore_bins illegal_bins import incdir include initial inout input inside instance int integer interface intersect join
join_any join_none
large liblist library local localparam logic longint
macromodule matches medium modport module
nand negedge new nmos nor noshowcancelled not notif0 notif1 null
or output
package packed parameter pmos posedge primitive priority program property protected pull0 pull1 pulldown pullup pulsestyle_onevent pulsestyle_ondetect pure
rand randc randcase randsequence rcmos real realtime ref reg release repeat return rnmos rpmos rtran rtranif0 rtranif1
scalared sequence shortint shortreal showcancelled signed small solve specify specparam static string strong0 strong1 struct super supply0 supply1
table tagged task this throughout time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef
union unique unsigned use
var vectored virtual void
wait wait_order wand weak0 weak1 while wildcard wire with within wor
xnor xor
/C2"System"
** 'b 'B 'o 'O 'd 'D 'h 'H 'sb 'sB 'so 'sO 'sd 'sD 'sh 'sH 'Sb 'SB 'So 'SO 'Sd 'SD 'Sh 'SH
** _
$assertkill $assertoff $asserton $async$and$array $async$nand$array $async$or$array $async$nor$array $async$and$plane $async$nand$plane $async$or$plane $async$nor$plane
$bits $bitstoreal $bitstoshortreal 
$cast $comment $countdrivers $countones
$date $dimensions $display $displayb $displayh $displayo $dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform $dumpall $dumpflush $dumpfile $dumplimit $dumpoff $dumpon $dumpports $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars
$enddefinitions $error $exit
$fatal $fdisplay $fdisplayf $fdisplayb $fdisplayh $fdisplayo $fell $feof $ferror $fflush $fgetc $fgets $finish $fopen $fmonitor $fmonitorb $fmonitorf $fmonitorh $fmonitoro $fclose $fread $fscanf $fseek $fsscanf $fstrobe $fstrobeb $fstrobef $fstrobeh $fstrobeo $ftell $fullskew $fwrite $fwriteb $fwritef $fwriteh $fwriteo 
$get_coverage $getpattern
$high $hold $history
$increment $incsave $info $input $isunbounded $isunknown $itor
$key 
$left $list $load_coverage_db $log $low 
$monitor $monitorb $monitorh $monitoro $monitoron $monitoroff 
$nochange $nokey $nolog $onehot $onehot0
$past $period $printtimescale
$q_add $q_exam $q_full $q_initialize $q_remove $q_random
$random $readmemb $readmemh $realtime $realtobits $recovery $recrem $removal $reset $reset_count $reset_value $restart $rewind $right $root $rose $rtoi
$sampled $save $scale $scope $sdf_annotate $set_coverage_db_name $setup $setuphold $sformat $shortrealtobits $showvariables $showscopes $showvars $signed $size $skew $sreadmemb $sreadmemh $sscanf $stable $stime $stop $strobe $strobeb $strobeh $strobeo $swrite $swriteb $swriteh $swriteo $sync$and$array $sync$nand$array $sync$or$array $sync$nor$array $sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane
$test$plusargs $time $timeformat $timescale $timeskew $typename $typeof
$ungetc $unit $unpacked_dimensions $unsigned $upscope $urandom $urandom_range
$value$plusargs $var $vcdclose $version
$warning $width $write $writeb $writeh $writeo $writememb $writememh

/C3"Operators"
->
+:
-:
@
@*
*>
,
;
.*
{
}
+
-
// /
*
**
%
>
>=
>>
>>>
<
<=
<<
<<<
!
!=
!==
&
&&
|
||
=
==
===
^
^~
~
~^
~&
~|
?
:
|->
|=>
/C4"Directives"
** `
`begin_keywords
`accelerate `autoexepand_vectornets
`celldefine
`default_nettype `define `default_decay_time `default_trieg_distributed `default_trireg_strength `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero
`else `elsif `endcelldefine `endif `end_keywords `endprotect `endprotected `expand_vectornets
`file
`ifdef `ifndef `include
`line
`noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive
`pragma `protect `protected
`remove_gatenames `remove_netnames `resetall
`timescale
`unconnected_drive `undef `uselib


/C5"DelaysAndParameters"
#
##

ultraedit wordfile for vhdl

/L15"VHDL" Line Comment = -- Nocase String Chars = " File Extensions = VHD VHO
/Delimiters = ~!@$%^&*()+=|\/{}[]:;""<> ,.?/
/Regexp Type = Perl
/Function String = "^\s*(\w*\s*:\s*process)"
/Function String 1 = "^\s*(entity\s+\w+)\s+is"
/Function String 2 = "^\s*(architecture\s*\w+\s+of\s*\w+)\s+is"
/Function String 3 = "^\s*(component\s*\w+)"
/Function String 4 = "^\s*(\w+\s*:\s*\w+)\s*$"
/Function String 5 = "^\s*(\w+\s*:\s*\w+)\s+port\s+map"
/Open Fold Strings = "(""process""if""loop" "component" "entity" "architecture"
/Close Fold Strings = ")""end process""end if""end loop" "end component""end entity" "end architecture"
/Open Brace Strings = "{" "(" "["
/Close Brace Strings = "}" ")" "]"
/C1"VHDL reserved words"
abs access after alias all and architecture array assert attribute
begin block body buffer bus
case component configuration constant
disconnect downto
else elsif end entity exit
file for function
generate generic group guarded
if impure in inertial inout is
label library linkage literal loop
map mod 
nand new next nor not null
of on open or others out
package port postponed procedure process pure
range record register reject rem report return rol ror
select severity signal shared sla sll sra srl subtype
then to transport type 
unaffected untis until use
variable
wait when while with 
xnor xor
/C2"VHDL attributes"
active ascending ascending 
base 
delayed driving driving_value
event 
falling_edge
high 
image instance_name 
last_active last_event last_value left leftof length low 
path_name pos pred 
quiet 
reverse_range right rightof rising_edge
simple_name stable succ 
transaction 
val value
/C3"VHDL stings"
""
/C4"VHDL types"
bit bit_vector boolean 
character
integer
line
natural
positive
real
signed std_logic std_logic_vector string
text time
unsigned
/C5"VHDL Procedures"
endfile
file_close file_open
read readline
write writeline

ultraedit wordfile for verilog

/L13"Verilog 1364-2001" Line Comment = // Block Comment On = /* Block Comment Off = */ String Chars = " File Extensions = V VL VMD
/Delimiters = ~!@%^&*()-+=|\/{}[]:;"<> , .?
/Regexp Type = Perl
/Function String = "^[ \t]*(config\s+\w+)"
/Function String 1 = "^[ \t]*(module\s+\w+)"
/Function String 2 = "^[ \t]*(task\s+\w+)"
/Function String 3 = "^[ \t]*(function[\s\[]*[^\]]*[\s\]]+\w+;)"
/Function String 4 = "begin\s*(:\s*\w+)"
/Function String 5 = "^[ \t]*([^(begin|else|assign|always|if)]\w+[ \t]+\w+\s*\()"
/Function String 6 = "^\s*(primitive\s+\w+" unfortunately ultraedit support but 6 Function String

/Open Fold Strings = "(" "begin" "function" "task" "module"
/Close Fold Strings = ")" "end" "endfunction" "endtask" "endmodule"
/Indent Strings = "begin" "fork" "specify" "config"
/Unindent Strings = "end" "join" "endspecify" "endconfig"
/C1"Keywords"
always and assign automatic
begin buf bufif0 bufif1
case casex casez cell cmos config
deassign default defparam design disable
edge else end endcase endconfig endmodule endfunction endgenerate endprimitive endspecify endtable endtask event
for force forever fork function
generate genvar
highz0 highz1
if ifnone initial inout input instance integer
join
large liblist library localparam
macromodule medium module
nand negedge nmos none nor noshowcancelled not notif0 notif1
or output
parameter pulsestyle_onevent pulsestyle_ondetect pmos posedge primitive pull0 pull1 pullup pulldown
real realtime reg release repeat rcmos rnmos rpmos rtran rtranif0 rtanif1
scalared showcancelled signed small specify specparam strength strong0 strong1 supply0 supply1
table task time tran tranif0 tranif1 tri tri1 tri0 triand trior trireg
use
vectored
wait wand weak0 weak1 while wire wor
xnor xor
/C2"System"
** 'b 'B 'o 'O 'd 'D 'h 'H 'sb 'sB 'so 'sO 'sd 'sD 'sh 'sH 'Sb 'SB 'So 'SO 'Sd 'SD 'Sh 'SH
** _
$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane
$bitstoreal
$countdrivers
$display $displayb $displayh $displayo
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform
$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars
$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite
$getpattern
$history $hold
$incsave $input $itor
$key
$list $log
$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro
$nochange $nokey $nolog
$period $printtimescale
$q_add $q_exam $q_full $q_initialize $q_remove
$random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi
$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane
$test$plusargs $time $timeformat $timeskew
$ungetc $unsigned
$value$plusargs
$width $writeb $writeh $write $writeo
/C3"Operators"
->
+:
-:
@
@*
*>
,
;
{
}
+
-
// /
*
**
%
>
>=
>>
>>>
<
<=
<<
<<<
!
!=
!==
&
&&
|
||
=
==
===
^
^~
~
~^
~&
~|
?
:
/C4"Directives"
** `
`accelerate `autoexepand_vectornets
`celldefine
`default_nettype `define `default_decay_time `default_trireg_strength `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero
`else `elsif `endcelldefine `endif `endprotect `endprotected `expand_vectornets
`file
`ifdef `ifndef `include
`line
`noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive
`protect `protected
`remove_gatenames `remove_netnames `resetall
`timescale
`unconnected_drive `undef `uselib
/C5"DelaysAndParameters"
#ay