System Verilog by example by example

System Verilog by example(constraint, random, covergroup)
module top;
typedef enum bit { BAD_PARITY, GOOD_PARITY } parity_e;
class packet_c;
rand bit [5:0] pkt_length;
bit[63:0][7:0] pkt_payload;
bit[7:0] parity;
rand parity_e parity_type;
function bit [7:0] calc_parity();
 calc_parity = { pkt_length, pkt_addr };
 for (int i = 0; i calc_parity ^= pkt_payload[i];
endfunction :calc_parity

function void randomize_payload();
 pkt_addr = $urandom ;
 pkt_length = $urandom ;
 for (int i=0; i < pkt_length; i ++)
  pkt_payload[i]= $urandom;
endfunction:randomize_payload

function void post_randomize();
  randomize_payload();  
  if (parity_type == GOOD_PARITY)
  parity = calc_parity();
  else
  do
  parity = $urandom;
  while (parity == calc_parity());
endfunction:post_randomize

endmodule

class packet_c;
typedef enum bit { BAD_PARITY , GOOD_PARITY } parity_e;
typedef enum bit[1:0] { SMALL,MEDIUM, LARGE } payload_e;
  constraint c { parity_type == GOOD_PARITY ;}
  constraint c1 { payload_type == LARGE ;}
  constraint c3 { pkt_addr == 2; }
  constraint length_range {
  (payload_type == SMALL) -> pkt_length inside { [1 : 20] };
  (payload_type == MEDIUM) -> pkt_length inside { [21 : 44]};
  (payload_type == LARGE) -> pkt_length inside { [45 : 63]};
  }
// Define the Coverage module for the packet defined
  covergroup cg @ (pkt_event);
  coverpoint pkt_length {
  bins usb_range = {[0 : 20]};
  bins pci_range = {[21 : 44]};
  bins ahb_range = {[45 : 63 ]};
  }
  coverpoint pkt_addr;
  coverpoint parity;
  endgroup