pins descriptionsA13,A12-A0:
Address inputs: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A10 LOW, bank selected by BA[2:0] or all banks (A10 HIGH).
The address inputs also provide the op-code during a LOAD MODE
command.
A13,A12-A0
Address inputs: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A10 LOW, bank selected by BA[2:0] or all banks (A10 HIGH).
BA0–BA2
Bank address inputs: BA[2:0] define to which bank an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. BA[2:0]
define which mode register, including MR, EMR, EMR(2), and
EMR(3), is loaded during the LOAD MODE command.
CK, CK#
Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQ and DQS/DQS#)
is referenced to the crossings of CK and CK#.
CKE
Clock enable: CKE (registered HIGH) activates
CS#
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder.
RAS#, CAS#,WE#
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
commandLOAD MODE (LM)
The mode registers are loaded via bank address and address inputs. The bank address
balls determine which mode register will be programmed.
RAS#/CAS#/WE#: L L L
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the bank address inputs determines the bank, and the
address inputs select the row. This row remains active (or open) for accesses until a precharge
command is issued to that bank. A precharge command must be issued before
opening a different row in the same bank.
RAS#/CAS#/WE#: L H H
READ
The READ command is used to initiate a burst read access to an active row. The value
on the bank address inputs determine the bank, and the address provided on address
inputs A0–Ai (where Ai is the most significant column address bit for a given configuration)
selects the starting column location. The value on input A10 determines whether
or not auto precharge is used.
RAS#/CAS#/WE#: H L H
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the bank select inputs selects the bank, and the address provided on inputs A0–Ai
(where Ai is the most significant column address bit for a given configuration) selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used.
RAS#/CAS#/WE#: H L L
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks.
RAS#/CAS#/WE#: L H L
REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-
before-RAS# (CBR) REFRESH.
RAS#/CAS#/WE#: L L H
CKE: previous H, now H
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down.
RAS#/CAS#/WE#: L L H
CKE: previous H, now L
Mode Register (MR)The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CAS latency, operating
mode, DLL RESET, write recovery, and power-down mode,
1.Burst length is defined by bits M0–M2,
The block is uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block.
2.Accesses within a given burst may be programmed to be either sequential or interleaved.
The burst type is selected via bit M3. sequential: use WRAP, and interleaved: grouped by 2
3.The normal operating mode is selected by issuing a command with bit M7 set to “0”. if 1, test mode and unpredicatable
4. DLL RESET is defined by bit M8, as shown in Figure 34 (page 77). Programming bit M8
to “1” will activate the DLL RESET function.
5. Write recovery (WR) time is defined by bits M9–M11.
6. Active power-down (PD) mode is defined by bit M12, which determines performance versus power savings.
7. The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 34 (page 77). CL is
the delay, in clock cycles, between the registration of a READ command and the availability
of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
Extended Mode Register (EMR)The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, ondie
termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable.
Posted CAS additive latency (AL) is supported to make the command and data bus efficient
for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL,
Graphs
Ball
DDR RAM State Machine
Hierarchical Diagram
Read Timing diagram
Write Timing diagram
Typical AC/DC characteristicstCK: 1.875~5 ns
CL: 7~3 tCK
TR and CP must have a minimum 500mV peak-to-peak swing.
Supply voltage Vdd: min 1.7, max 1.9 V
DC differential input voltage Vid(DC): min 250, max VddQ (mV)
Input high (logic 1) voltage: min Vih(DC), max Vref(DC) + 125 VddQ1 (mV)
