sdc cmd

Synopsys Design Constraint (SDC)

Synopsys Design Constraints (SDC) is a format used to specify the design intent, including the timing and area constraints for a design. SDC is based on the tool command language (Tcl). The Synopsys Design Compiler and PrimeTime tools use the SDC description to synthesize and analyze a design. In addition, these tools can generate SDC descriptions for and read SDC descriptions from thirdparty tools.

file format

SDC is a Tcl-based format. All commands in an SDC file conform to the Tcl syntax rules.
You use an SDC file to communicate the design intent, including timing and area requirements between EDA tools. An SDC file contains the following information:
• The SDC version (optional)
• The design constraints
• Comments (optional)

Limitations(?):Constraints imported from one SDC file will be discarded if a second SDC file is imported. All constraints must be imported from a single SDC file.

file version

set sdc_version value
If the SDC file does not specify a version, the Synopsys tools assume that the file uses version 1.4

SDC Constraint Commands

Type of information Commands
Operating conditions 
  set_operating_conditions
Wire load models 
  set_wire_load_min_block_size
  set_wire_load_mode
  set_wire_load_model
  set_wire_load_selection_group
System interface 
  set_drive
  set_driving_cell
  set_fanout_load
  set_input_transition
  set_load
  set_port_fanout_number
Design rule constraints 
  set_max_capacitance
  set_max_fanout
  set_max_transition
  set_min_capacitance
Timing constraints 
  create_clock
  create_generated_clock
  set_clock_gating_check
  set_clock_latency
  set_clock_transition
  set_clock_uncertainty
  set_data_check
  set_disable_timing
  set_input_delay
  set_max_time_borrow
  set_output_delay
  set_propagated_clock
  set_resistance
Timing exceptions
  set_false_path
  set_max_delay
  set_min_delay
  set_multicycle_path
Area constraints
  set_max_area
Power constraints
  set_max_dynamic_power
  set_max_leakage_power
Porosity constraints
  set_min_porosity
Logic assignments
  set_case_analysis
  set_logic_dc
  set_logic_one
  set_logic_zero
SDC Design Objects
Design object Access command Description
design
 current_design A container for cells. A block.
clock1
 get_clocks A clock in a design.
 all_clocks All clocks in a design.

port
 get_ports An entry point to or exit point from a design.
 all_inputs All entry points to a design.  
 all_outputs All exit points from a design.  

cell
 get_cells An instance of a design or library cell.
pin
 get_pins An instance of a design port or library cell pin.
net
 get_nets A connection between cell pins and design ports.
library
 get_libs A container for library cells.
lib_cell
 get_lib_cells A primitive logic element.
lib_pin
 get_lib_pins An entry point to or exit point from a lib_cell.

Validating SDC Files
To validate the syntax of an SDC file, use the read_sdc -syntax_only command in either Design Compiler or PrimeTime. The read_sdc -syntax_only command generates warning
messages if your SDC file contains unsupported commands or arguments.

Clock Constraint

create_clock -period period_value [-name clock_name] [-waveform edge_list] [port_pin_list]

period_value (specified in ns) is mandatory. There will be no clock created if the period is not supplied.
clock_name is optional. It is unnecessary if port_pin_list contains one name. edge_list is optional

port_pin_list may contain either zero names or one name

Max Delay Constraint
The set_max_delay constraint sets the path delay of the specified ports to a restricted value. The syntax is as follows:
set_max_delay [-from from_list] [-to to_list]
delay_value
• from_list is mandatory
• to_list is mandatory
• delay_value is specified in ns