Supported SystemVerilog Keywords:
always_comb, always_ff, always_latch, assert, bit byte, const, do, endinterface, enum, import, int, interface, logic, longint, modport, packed, priority, shortint, struct, typedef, unique.
Unsupported SystemVerilog Keywords:
assume, break, continue, endproperty, endsequence, expect, property, return, sequence, timeprecision, timeunit, union, void.
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